1. Field of the Invention
The present invention relates to a digital signal receiver. More specifically, the present invention relates to a digital signal receiver such as a teletext receiver adapted for displaying characters on a screen by extracting a digital signal including a clock run-in signal, a framing code signal and a data signal inserted in the vertical blanking period of a television signal of character multiplex transmission.
2. Description of the Prior Art
Character multiplex broadcasting has been proposed as a digital signal transmission system for use with television receivers. Such system is adapted such that a digital signal representing data such as characters and figures is inserted in an appropriate period of one to several horizontal scanning periods during a vertical blanking period of a television broadcasting signal so that the digital signal may be transmitted.
A receiver adapted for receiving such television character multiplex broadcasting is described in detail in an article entitled "Teletext Receiver and Test Signal Generating Apparatus" contributed by Mr. Kuroda et al. in Sanyo Technical Review, Vol. 11, No. 1, 1979. The above referenced article describes the rating of such teletext signal and an outline of a receiver. Another article entitled "Consumer Text Display Systems" contributed by Brian Harden in IEEE Transactions on Consumer Electronics, July, 1979, Vol. CE 25 also describes an overall structure of a teletext system.
FIG. 1 is a view showing a structure of a television character multiplex signal, representing one horizontal scanning period of the 20th horizontal scanning period during the vertical blanking period where a digital character signal (data) is inserted. More specifically, a digital signal is inserted in one horizontal scanning period of the 20th period during the vertical blanking period. The digital signal includes a clock run-in signal, a framing code signal and a data signal. The clock run-in signal starts a predetermined time period after a color burst signal (CG) positioned at the back porch of a horizontal synchronizing signal (HS) and includes a repetition of the logics one and zero. The framing code signal includes an 8-bits signal following the clock run-in signal and the data signal lasts from the next bit of the framing code signal to the end of the above described one horizontal scanning period.
The above described data signal (DA) includes a bit serial code signal covering 8-bits as one word. The above described clock run-in signal is structured as a signal of 16 or 18 bits including a repetition of the logics one and zero as described previously and is used as a time reference in generating a sampling clock signal for extracting the above described data signal (DA) in a television receiver. The above described framing code signal comprises a specified code signal of 8-bits selected to achieve proper synchronization even upon occurrence of a data error of one bit and is used as a time reference in conversion from serial to parallel on an 8-bit by 8-bit basis of the data signal extracted through sampling. Since the framing code signal includes a number of utilizable code structure any suitable one may be employed. For example, the C55 system of NHK in Japan adopts "11100101" and the Teletext system in United Kingdom "11100100" and the Antiope system in France adopts "11100111".
FIG. 2 is a block diagram showing of a conventional digital signal receiver for receiving a character multiplex broadcasting signal and FIG. 3 is a graph showing an overall group delay characteristic of a transmission path between a transmitter and a receiver.
Now referring to FIG. 2, a structure and an operation of a conventional digital signal receiver. A television signal transmitted from a transmitter end, not shown, is applied through an antenna to a tuner 1. The tuner 1 is selectively tuned to a desired television signal and the desired television signal is converted into a video intermediate frequency signal. The video intermediate frequency signal from the tuner 1 is applied to a video intermediate frequency circuit 2. Although not shown, the video intermediate frequency circuit 2 comprises a video amplifier, a video detecting circuit and the like and provides a video signal. The video signal from the video intermediate frequency circuit 2 is applied to a video processing circuit 11 and a gate circuit 3. The gate circuit 3 serves to extract from the video signal one horizontal scanning period portion of the character multiplex signal as inserted. The output signal from the gate circuit 3 is applied to a slicer circuit 4. The slicer circuit 4 serves to slice the output signal from the gate circuit, thereby to convert the same into a rectangular waveform for the purpose of providing a binary signal. The output signal from the slicer circuit 4 is applied to serial/parallel converting circuits 5 and 8 and a frequency dividing circuit 103 included in a sampling clock generating circuit 10. The sampling clock generating circuit 10 serves to generate a sampling clock signal in synchronism with a clock run-in signal included in the output signal from the slicer circuit 4 and comprises a quartz oscillator 101, an oscillating circuit 102, a frequency dividing circuit 103 and a phase shifting circuit 104. The oscillating circuit 102 is for making oscillation of a signal of say 28 MHz and the frequency dividing circuit 103 serves to frequency divide by 1/5 the oscillation output signal from the oscillating circuit 102 in synchronism with the output signal from the slicer circuit 4. The frequency divided output signal from the frequency dividing circuit 103 is applied to the phase shifting circuit 104 as a sampling clock signal. The phase shifting circuit 104 is produced for adjusting the phase of the sampling clock signal. The sampling clock signal thus generated is applied to the above described serial/parallel converting circuits 5 and 8.
The serial/parallel converting circuit 8 serves to convert the framing code signal of 8 bits into a parallel signal, which is then applied to a comparator 9. The comparator 9 determines coincidence of the preset code signal obtained from a memory stored with the framing code signal obtained from the serial/parallel converting circuit 8, thereby to provide a timing pulse upon coincidence of both, which is applied to a byte synchronization gate circuit 6 and a digital processing circuit 7.
The above described serial/parallel converting circuit 5 includes a shift register and is responsive to the sampling clock signal from the above described sampling clock generating circuit 10 to extract the data signal on an 8-bit by 8-bit basis from the output signal of the slicer circuit 4 by sampling the same, whereby the data signal of 8 bits, i.e. one byte as extracted is converted into a parallel signal. The data signal as converted into the parallel signal by the serial/parallel converting circuit 5 is byte synchronized for every 8 bits by the byte synchronizing gate circuit 6 as a function of the timing pulse obtained from the comparator 9. The data signal as byte synchronized is applied to the digital processing circuit 7. The digital processing circuit 7 comprises a microcomputer, for example, and digitally processes the data signal of 8 bits (one byte) so that the same is displayed on a proper position on the television screen. The digital processing circuit 7 is more fully described in the previously described two articles. The data signal as processed by the digital processing circuit 7 is applied to the video processing circuit 11. The video processing circuit 11 serves to superimpose the data serving as a character signal as processed by the digital processing circuit 7 on to the television video signal obtained from the video intermediate frequency circuit 2 and provides the same to a picture tube 12.
A conventional digital signal receiver is generally structured as described above. A point to be noted in connection with the present invention is an overall group delay characteristic of a transmission path from a modulator on the part of a transmitting station through the tuner 1 to the output point A of the video intermediate frequency circuit 2 in the receiver. More specifically, generally a television receiver is adapted such that the group delay characteristic from the tuner 1 through the video intermediate frequency circuit 2 may be offset by the group delay characteristic on the part of the transmitter. However, this is true only with respect to a wide range component (3 to 4 MHz band) in the video signal range and no particular consideration has not been necessarily given to the low frequency range portion (0 to 2 MHz band) in the video signal range. Accordingly, the low frequency range portion of the group delay characteristic at the point A in FIG. 2, i.e. the overall group delay characteristic of the transmission path including the transmitter and the receiver (the low frequency range group delay characteristic) could be flat as shown as (A) in FIG. 3, could be slanted as shown as (B) in FIG. 3 meaning a lagged phase, or could be slanted as shown as (C) in FIG. 3, meaning an advanced phase, depending on the cases. This is determined by the respective group delay characteristics of the transmission path from the modulator on the part of the transmitter and the tuner 1 through the video intermediate frequency circuit 2 in the receiver.
Meanwhile, the above described bit rate of the character multiplex signal is selected to be 5.73 Mbits/second in the case of the preferably described C55 system of NHK, for example. Therefore, in the case of a repetition of the logics one and zero for each bit such as in the previously described clock run-in signal, the repetition frequency comes to correspond to a half of the bit rate, i.e. approximately 2.86 MHz. This means that the clock run-in signal is little influenced by the lower frequency range portion (0 to 2 MHz frequency range) of the group delay characteristic shown in FIG. 3.
On the other hand, the bit rate of the framing code signal in the character multiplex signal is also 5.73 Mbits/second as a matter of course. However, the framing code signal is not a signal of periodical repetition for each bit as described previously. This means that the framing code signal includes a frequency component relatively low, i.e. lower than 2 MHz. Accordingly, the framing code signal is influenced by the low frequency region group delay characteristic shown as (B) or (C) in FIG. 3, thereby to cause a waveform distortion and a phase distortion. Therefore, the framing code signal can not be properly sampled in the serial/parallel converting circuit 5 and the comparator 9 shown in FIG. 2 cannot detect coincidence of the predetermined code signal and the framing code signal and hence a problem is involved that an error is caused in achieving byte synchronization of the data signal.
More specifically, when a waveform distortion is caused in the framing code signal, the level of the distorted portion which was to be determined as the logic one decreases and that portion is determined as the logic zero in the slicer circuit 4 and hence is not sliced. Therefore, according to a conventional digital signal receiver, when the framing code signal is sampled in the serial/parallel converting circuit 8 as a function of the sampling clock signal, an error is caused in the first bit or the final bit out of three bits which must originally assume the high level consecutively at the beginning of the framing code signal, with the result that the framing code cannot be detected. Furthermore, when a phase distortion is caused in the framing code signal, the phase could be lagged or advanced. However, since the clock run-in signal is little influenced by the low frequency range group delay characteristic of the transmission path, no change occurs in the phase of the sampling clock signal being generated in synchronism with the clock run-in signal. This means that the phase of the framing code signal with respect to the sampling clock signal changes. More specifically, the sampling time of the framing code signal being sampled with the sampling clock signal deviates, with the result that an erroneous framing code signal is detected and a normal framing code signal is not detected. This causes an error not only in connection with the framing code signal but also in connection with the data when the succeeding data signal is sampled.